Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /AES0 /AES_RXDS_DELAY

A delay added to the OSPI RXDS input signal in 0.5-ns steps. The maximum allowed value to program is 16. NOTE: The delay should be set to overcome the internal 3.6 ns delay of OSPI data lines compared to the RXDS line. The objective is to ensure that RXDS is delayed by 1/4 OSPI clock cycle with respect to the leading edge of the valid data lines. The nominal delay code for 100 MHz operation should be set to 12, resulting in approximately 6 ns delay for the RXDS line. This value may need to be calibrated for each specific application.

0 (Val_0x0): No delay

1 (Val_0x1): 0.5 ns delay

2 (Val_0x2): 2 x 0.5 ns delay

15 (Val_0xF): 15 x 0.5 ns delay

16 (Val_0x10): 16 x 0.5 ns delay